1. Field of the Invention
The present invention is used in a memory device and relates to a circuit for logic processing.
More specifically, the invention particularly relates to a memory circuit of a logic gate circuit increasing levels of input logic signals and providing AND (NAND) logic output of the input signals, being preferably used for a test circuit for executing parallel tests of a memory cell (multi-bit test).
Further, the invention particularly relates to a memory circuit of a sense circuit selecting and amplifying output data of a memory cell selected from plural memory cells corresponding to one line of an output data bus of a semiconductor memory device, in accordance with a read out address.
Furthermore, the invention particularly relates to a memory circuit having a sense circuit selecting output data, in accordance with a read out address, by processing a wired-OR operation of outputs of each of pre-sense amplifiers for amplifying outputs of each group of memory cells, all memory cells being divided into plural groups.
2. Description of the Related Art
Conventionally, for such a semiconductor memory device having a comparatively large memory capacity and high speed operation performance as an SRAM, BiCMOS-SRAM, etc., a test of data writing in and reading out is carried out for the whole group of memory cells in order to confirm the operations of all memory cells arranged in an array composition. Such a test does not need much time if a memory capacity of a semiconductor memory device is comparatively small. However, recently the memory capacity of a semiconductor memory devices, that is, the number of memory cells, has considerably increased, and the time required for the test has greatly increased. As such, the test becomes a much time consuming task.
On the other hand, parallel test circuits of memory cells (multi-bit test) have lately developed for solving the problem of increase of the test time, by executing the test for a group of memory cells in parallel.
In FIG. 8, an example of conventional parallel test circuits executing the multi-bit test is shown. The example conventional parallel test circuit has such a structure that the third ECL circuit 60 is put on the first and the second ECL circuits 58 and 59, as the test circuit 54 is viewed from the side of a power line. Then, if a voltage of the power source decreases, for example, near to 2.5 V, operational margins of the two bipolar transistors are lost, which causes such a problem that a correct XOR processing of input signals can not be executed and the parallel test (multi-bit test) becomes impossible.
In the following, the above-mentioned problem is explained more in detail. Signals sent in a pair of common data bus lines 51 are distributed and sent to the test circuit 54 and MSA 53 via a signal distributing circuit 52. Voltages of the distributed signals A and B to the test circuit 54 are reduced by 2.times. Vbe (where Vbe is a voltage decrease between a base and an emitter of a transistor) from a voltage of a higher side power source (Vcc). Then, since a voltage margin of 2.times. Vbe is needed for the two stages of the bipolar transistors and the voltage margin of Vs for the third ECL circuit 60, in the test circuit 54, the operational voltage of (4.times.Vbe+Vs) is totally required. If Vbe is 0.8 V and Vs is 0.4 V, then the needed operational voltage is 3.6 V (=0.8.times.4+0.4).
As mentioned above, if the voltage of a power source decreases near to 2.5 V in the parallel test circuit of memory cells, an correct XOR processing of input signals can not be executed, and consequently the parallel test of memory cells (multi-bit test) becomes impossible.
The above-mentioned point is true, but it is possible to provide only one stage of the emitter follower by reducing the number of the emitter followers to the input nodes of the test circuit 54, in the above-mentioned parallel test circuit of memory cells. However, even by using only one stage of the emitter follower, since the required operational voltage of the test circuit 54 is 2.8 V, a correct XOR processing of input signals can not be also executed, consequently the parallel test of memory cells (multi-bit test) becomes impossible if the voltage of a power source decreases near to 2.5 V.
Further, chip area has been is increasing according to the large increase of the memory capacity of a semiconductor memory device, and the wiring length in a chip, of a data bus for data reading out, becomes longer. Since a resistance R and a parasitic capacitance of the wiring in a chip increases in accordance with increase of the wiring length, the signal transmission delay by the wiring becomes larger, which impedes a high-speed data access.
Then, in order to decrease the parasitic capacitance by the data bus wiring of a sense circuit after a pre-sense amplifier, it is devised that an output signal of a collector node in a current switch of ECL (Emitter-Coupled Logic) included in a pre-sense amplifier is output to a data bus from an emitter node via an emitter follower (ISSCC, 91(SESSION 3/HIGH-SPEED RAM/PAPER WP 3.5)). Since the parasitic capacitance of a collector is considerably smaller than that of an emitter, which is clear from the structure of a bipolar transistor, the parasitic capacitance by the data bus wiring of a sense circuit after a pre-sense amplifier can be reduced by outputting the output signal from an emitter node.
Then, by the above conventional technique, a control circuit is provided to a base, for controlling the voltage of a base of an emitter follower in an output part of a pre-sense amplifier, and the voltage thoroughly lower than the usual signal level is applied to the base of an emitter follower in the pre-sense amplifier not including the memory cell corresponding to an address of the data to be read out. Therefore, since the difference between the transistor state in the case of including the selected memory cell and that in the case of not including the one clearly appears in the level of the output voltage (emitter voltage) of the outputting emitter follower, the output signals of the selected memory cell can be easily selected or specified by the wired-OR-logic operation of the output signals of the plural pre-sense amplifiers.
Then, it is possible to compose a sense circuit having a hierarchical structure wherein plural pre-sense amplifiers are adequately divided into plural groups, and the wired-OR-logic of the output signals in each one of the groups is executed, and further the wired-OR-logic operation of the outputs of the wired-OR-logic operation of the groups via an emitter follower is executed and the wired-OR-logic operation is repeated by several stages. Therefore, by dividing the data bus lines of a sense circuit hierarchically into multi-stages, the RC delay can be reduced. To be more precise, the RC delay is decided by the RC between the former stage of an emitter follower and the present stage of an emitter follower, the wiring length between the two stages of emitter followers is effectively reduced.
However, the output voltage of an emitter of an emitter follower is reduced by the voltage decrease of Vbe (for example, about 0.8 V) between a base and a emitter, to the signal level input to a base of the emitter follower. Then, if the wired-OR-logic operation of signals divided into multi-stages is sequentially executed via multi-stages of emitter followers, the signal voltage is largely decreased. And, sometimes, the signal voltage decreases under the lower limit operational voltage of a sense amplifier provided at the final stage or the next stage of an emitter follower. For example, in case a sense amplifier is composed by using a current switch of ECL, the lower limit level of an input signal input to the current switch is 1.2 V where the voltage decrease between a base and an emitter is 0.8 V and the required minimum operational voltage of a constant current source connected to an emitter of the current switch is 0.4 V. Therefore, if the voltage of a power source of a memory apparatus is 3.3 V, it is impossible to compose more than 3 stages of the wired-OR- logic via an emitter follower including an emitter follower of the output part of each pre-sense amplifier, which restricts the realization of many stages of the data bus lines and further the high-speed data access.
On the other hand, if it is intended to decrease the power voltage for reducing the consumed power, the high-speed data access is impeded since the realization of many stages of the data bus lines is restricted.
Further, there is a method of increasing the signal voltage decreased in an emitter follower by a shift-up circuit using a current switch. However, the voltage signal increased by a current switch has a constant level independent of the level of an input signal. Therefore, the output signal of the selected pre-sense amplifier can not be distinguished from the output signals of the other non-selected pre-sense amplifiers since the increased level of the selected output signal has the same level as the non-selected output signals in spite of having a level higher than those of the other output signals before being increased. That is, since the original relative level relations among the output signals of the pre-sense amplifiers are lost, the output signals from the selected memory cell can not be specified by executing the wired-OR-logic operation of the output signals increased by the current switches, of the pre-sense amplifiers. Therefore, in the case of increasing the output signals by the current switches, the sense circuit becomes complicated since a logic circuit for specifying the output signals from the selected pre-sense amplifier among the increased output signals is necessary.